OM3200 [STM-1/4/16 Multi Service Flexible Multiplexer]

The FlexMux is a highly integrated, ultra compact Flexible Single Chip Multiplexer ‘Virtual ASSP' targeted to the Xilinx Spartan-3, Spartan-6, Virtex-5 and Virtex-6 family. It can be tailored quickly and easily to meet the interface demands of your application and is available as either a vASSP for standalone applications or IP for integration in larger designs.


The FlexMux has been designed from the ground up as cost-effective ASSP replacement in an FPGA - ultra-compact IP targeting the lowest-cost FPGA, highly integrated design with Framer, Mapper and Interface modules all in a single package. In addition, support for 16 bit wide DDR2 for external packet buffer and external differential delay memory (up to 64ms), provision of a Software Device Driver and on-chip diagnostic facility and supporting toolset, all lead to lower cost and accelerated TTM.


The FlexMux supports build configurations of up to 2x STM16/4/1 (OC48/12/3) or 4x STM4/1 (OC12/3) or 16 x STM1 (OC3) ports on the network side and any combination of up to 8 Fast Ethernet or up to 4 Gigabit Ethernet ports and up to 64 direct E1 or T1 channels on the client side. The Client ports may also be extended using build selectable channelized interfaces such as Byte Stream Bus for PDH and SPI-3 for Ethernet. Up to 1344 PDH channels and 256 Ethernet channels may be supported. Architectural consideration has being given to how the number of Ethernet Channels may be extended up to 672 which would require 672 VCAT Groups and a SPI3 interface capable of supporting 672 channels.

The FlexMux supports both Terminal Mode (APS/MSP) and Ring Mode (UPSR/SNCP) network configurations. The Ring block supports drop and insert of both high and low order payloads for applications where the FlexMux is deployed in SNCP / UPSR ring networks. Any high order or low order path, which is not locally added and dropped, may be forwarded to the same timeslot on the mate SDH / Sonet port. Timeslot Interchange (TSI) is not supported for traffic forwarded by the Ring block.


The Ring block can optionally support Drop and Continue connections.


The Ring block may be omitted for applications which do not require through connection between SDH / Sonet ports, e.g. APS / MSP network applications. The Ring block is required to be included in applications requiring byte synchronous mapping of E1s or bit synchronous mapping of T1s.


For the FE/GE ports, each port can be independently configured to use real or virtual concatenation up to the bandwidth of the port. When using virtual concatenation, LCAS is supported to allow bandwidth management and recovery from network faults.


Up to 64 Direct E1/T1 interfaces and up to 1344 logical E1/T1 interfaces using the channelized Byte Stream Bus are supported. Each channel is independently configurable between E1 and T1.

 
On ingress, the STM-1/4 Framer provides Framing, section overhead termination, high order pointer processing and high order path overhead termination or monitoring. On Egress it provides high order pointer generation, optional path overhead insertion and section overhead insertion. All high order paths can be processed simultaneously.

The Low Order block provides low order pointer processing and POH termination on Ingress for any path which is terminated in the FlexMux. On Egress it provides low order pointer generation and optional path overhead insertion for any locally added low order payload


OmniSpy is the Omiino development support tool. It provides a user interface on development boards, and assists board bring-up and software debugging during development and integration.

 

STM-1/4/16 OC-3/12/48 Line Interface Module

  • Up to 2x STM16/4/1 (OC48/12/3) or 4x STM4/1 (OC12/3) or 16x STM1 (OC3).
  • A1A2 framing/frame delineation performed in accordance with G.707 and GR-253-CORE.
  • Frame scrambling/descrambling performed in accordance with G.707 and GR-253-CORE.
  • SDH mappings - AU4-4c, AU4 and AU3 supported.
  • Sonet mappings - STS-1, STS-3c, STS-12c SPE supported.
  • SDH payloads - VC-11, VC-12, VC-2, VC-3, VC-4, VC-4-4c supported.
  • Sonet payloads -, VT1.5, VT2, STS1, STS-3c, 12c supported.
  • Full SOH termination/generation supported.
  • HO pointer processing/pointer generation performed in accordance with G.707 and GR-253-CORE.
  • Full HO POH termination/optional insertion supported. 

Low Order Module

  • SDH mappings - TUG Structured AU4 and AU3 supported.
  • VC-3 (TU-3), VC-2 (optional), VC-12 and VC-11 Low Order payloads supported.
  • Sonet mappings - VT structured STS-1 supported.
  • VT6 (optional), VT3 (optional), VT2 and VT1.5 Low Order payloads supported.
  • LO pointer processing/pointer generation performed in accordance with G.707 and GR-253-CORE.
  • Full LO POH termination/optional insertion supported. 

UPSR / SNCP Ring Module

  • Support for Terminal Mode (APS/MSP) and Ring Mode (UPSR/SNCP).
  • 100 % through traffic capability.
  • Full path monitoring of working & protection for all dropped paths.
  • Protection switching based on : xU-LOP, xU-AIS, xP-UNEQ, xP-TIM, xP-PLM, H4-LOM

E1/T1 PDH Mapper Module

  • Support for 1-1344 E1 or T1 channels with standard module, other port counts available on request.
  • Each channel individually rate selectable between E1 and T1.
  • Each channel individually framing mode selectable between Unframed, FAS (E1), SF (T1), ESF (T1).
  • Support for mapping of framed or unframed E1 into VC-12/VT2.
  • Support for mapping of framed or unframed T1 into VC-11/VT1.5.
  • E1 Framers on ingress and egress for LOF and CRC-4 error detection.
  • T1 Framers on ingress and egress for LOF and CRC-6 error detection (ESF framing).
  • Support for Asynchronous ‘mapping mode' of E1 and T1.
  • Support for Byte Synchronous ‘mapping mode' of E1 and T1 when used with Framer and UPSR/SNCP Ring module.
  • Support for Bit Synchronous ‘mapping mode' of ESF framed T1 when used UPSR/SNCP Ring module.
  • Clock and Data (NRZ) interface to external LIUs.
  • Ability to control serial bus LIUs from FlexMux (specific devices TBD.)
  • Support for LOS and CV detection by LIU.
  • [OPTIONS]
  •  J1 support available as an option.
  • E1 only available as an option (with significantly lower memory requirements.).
  • Mapper only variant, without framers, available as an option.
  • Optional PDH Jitter attenuator to support low cost LIUs.
  • Multiplexed byte wide internal interface available for user logic.

FE/GE Vcat/LCAS Mapper Module

  • Support for direct or channelized Ethernet interfaces.
  • Phy interface using (G)MII with dedicated MACs for each channel.
  • Up to 1344 Channelised ports using proprietary interface.
  • Up to 256 Channelised ports using SPI3.
  • Pause frame support (pause request only).
  • 2KB Jumbo frame support (10KB available as on option).
  • Ethernet statistics support ( good/bad frames/octets, dropped packets)

Ethernet Mappings

  • Support for GFP-F and optionally HDLC (POS/LAP-S) mapping.
  • GFP statistics support (Good / Bad frames, cHEC error counts).

VCAT Groups

  • Each VCAT Group can be independently configured to support LCAS or no LCAS.
  • External 16bit DDR-2 Differential delay memory.

Supported Concatenation Payloads

  • Real concatenated SDH/PDH payloads VC4-16c, VC-4-4c, VC-4, VC-3 (AU-3), VC-3 (TU-3), VC-12, VC-11 and E1.
  •  Real concatenated Sonet payloads STS-48c, STS-12c, STS-3c, STS-1, VT2, VT1.5 and T1.
  • Virtually concatenated SDH payloads.
  • Virtually concatenated Sonet payloads.
  • Optional support for VC-2, VT6 and VT3 payloads.

Line Interface

  • Direct connection to Optics with internal CDR.

Client Interfaces

  • Byte Stream Bus for high channel count E1/T1/J1 applications.
  • Direct connection to LIU for low channel count E1/T1/J1 applications.
  • SPI4.2/ SPI3 for high channel count Ethernet applications.
  • Direct connection to PHY for low channel Ethernet Applications

Click here to download the OM3200 Datasheet